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Cypress Semiconductor /psoc63 /GPIO /PRT[11] /CFG_IN

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Interpret as CFG_IN

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CMOS)VTRIP_SEL0_0 0 (VTRIP_SEL1_0)VTRIP_SEL1_0 0 (VTRIP_SEL2_0)VTRIP_SEL2_0 0 (VTRIP_SEL3_0)VTRIP_SEL3_0 0 (VTRIP_SEL4_0)VTRIP_SEL4_0 0 (VTRIP_SEL5_0)VTRIP_SEL5_0 0 (VTRIP_SEL6_0)VTRIP_SEL6_0 0 (VTRIP_SEL7_0)VTRIP_SEL7_0

VTRIP_SEL0_0=CMOS

Description

Port input buffer configuration register

Fields

VTRIP_SEL0_0

Configures the pin 0 input buffer mode (trip points and hysteresis)

0 (CMOS): Input buffer compatible with CMOS and I2C interfaces

1 (TTL): Input buffer compatible with TTL and MediaLB interfaces
VTRIP_SEL1_0

Configures the pin 1 input buffer mode (trip points and hysteresis)
VTRIP_SEL2_0

Configures the pin 2 input buffer mode (trip points and hysteresis)
VTRIP_SEL3_0

Configures the pin 3 input buffer mode (trip points and hysteresis)
VTRIP_SEL4_0

Configures the pin 4 input buffer mode (trip points and hysteresis)
VTRIP_SEL5_0

Configures the pin 5 input buffer mode (trip points and hysteresis)
VTRIP_SEL6_0

Configures the pin 6 input buffer mode (trip points and hysteresis)
VTRIP_SEL7_0

Configures the pin 7 input buffer mode (trip points and hysteresis)

Links

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Register License

Copyright 2016-2018 Cypress Semiconductor Corporation \n Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License.
You may obtain a copy of the License at \n
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and
limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data